1. Field of the Invention
The present invention generally relates to a driving technique for a liquid crystal display (LCD), in particular, to a source driving and gate driving technique.
2. Description of Related Art
LCDs, especially thin film transistor (TFT) LCDs, have been widely utilized. Images on an LCD are displayed by a pixel array formed of a plurality of pixels, and each pixel displays a corresponding colour according to a time sequence of a frame. In order to drive the pixel display, various control signals are required, and usually a gate driver and a source driver are used to perform intersection control.
The conventional TFT LCD adopts a hold-type image display mode. Whenever a pixel voltage is written, a frame period is kept, but this display mode may lead to fuzzy dynamic images. Therefore, the conventional art then proposes an impulse-type driving technique to effectively eliminate the aforementioned defect.
FIG. 1 is a schematic view showing the architecture of a panel system of the conventional TFT LCD. Referring to FIG. 1, the TFT LCD has a display panel 100, and a pixel array constituted by a plurality of pixels 102 is formed on the display panel 100. In order to drive the pixels 102, generally the pixel grey-scale data to be displayed are input through a source driver 106. A gate driver 104 is used to activate scan lines in sequence, such that the pixels will display the pixel grey-scale data. The gate driver 104 and the source driver 106 are controlled by a timing controller 108.
FIG. 2 shows timing control of a conventional driving method. Referring to FIGS. 1 and 2, generally, the operation includes an interface with a data transmission mode of reduced swing differential signaling (RSDS) or mini-low-voltage differential signaling (mini-LVDS). The timing controller 108, for example, respectively sends a set of control signals 110 such as STH/TP/RVS timing control signals and the pixel data to the source driver 106, in which STH is particularly adopted for the RSDS transmission mode. In addition, the timing controller 108 also sends STV/CPV/OE and other timing control signals 112 to the gate driver 104, for sequentially controlling the voltage required by all the pixel capacitors on the TFT LCD panel 100, and the panel 100 shows different grey-scale variations according to different applied voltages. As shown in the figure, the input sequence of the pixel driving data is pn(x,y)  pn(x+1,y)  pn(x+2,y) . . . pn(x,y+1)  pn(x+1,y+1)  pn(x+2,y+1) . . . pn+1(x,y)  pn+1(x+1,y)  pn+1(x+2,y ) . . . pn+1(x,y+1)  pn+1(x+1,y+1)  pn+1(x+2,y+1) . . . , that is, the input is carried out in sequence along a single direction. A detailed implementation of the above scan mode is that the source driver 106 is used to sequentially transmit synchronous signals in a horizontal direction and the gate driver 104 is used to sequentially transmit synchronous signals in a vertical direction, such that the horizontal synchronous signals of the source driver 106 and the vertical synchronous signals of the gate driver 104 are serially-connected by stages.
STH is a horizontal synchronous signal of the RSDS data type source driver. For the mini-LVDS data type, the horizontal synchronous signals of the source driver 106 are contained in the data. TP is a voltage output control signal of the source driver 106, and RVS is a voltage polarity designating signal of the source driver 106. STV is a vertical synchronous signal of the gate driver 104. CPV is a clock signal of the gate driver 104. OE is an output enable control signal. As shown in FIG. 1, OE is connected to all the gate drivers 104, so the output enables of all the gate drivers are the same.
However, in accordance with different driving mechanisms, the above driving manner is not the only feasible way. Those in the art continuously search for other more flexible driving manners to go with other different operating mechanisms.